Method for sample and hold a signal and flat pannel driving method using the same
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United States of America Patent
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Issued Date -
Dec 21, 2006
app pub date -
Jun 20, 2005
filing date -
Jun 20, 2005
priority date (Note) -
Abandoned
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Abstract
A sample-and-hold circuit is provided for an input voltage in response to a timing signal and outputting a holding voltage. The sample and hold circuit includes a plurality of switches, first and second capacitors, first and second differential input units, and an output unit. One of the switches which is controlled by a switching signal is used for preventing the voltage outputted by the output unit from being back to the inverting input terminal of the first differential input unit while the voltage of the input signal is being transferred to the first node. One of the switches which is controlled by the switching signal is used for preventing the voltage outputted by the output unit from being back to the inverting input terminal of the second differential input unit while the voltage of the input signal is being transferred to the second node.
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