Assembly structure and method for chip scale package
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United States of America Patent
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Issued Date -
Dec 7, 2006
app pub date -
Jun 4, 2005
filing date -
Jun 4, 2005
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Disclosed is an assembly structure of chip scale package, which can effectively avoid various yield and quality problems resulted from the poor control of epoxy during the process of chip scale package. A buffer zone whose planar size is smaller than that of the chip is disposed on the substrate, and the chip is then affixed to the buffer zone utilizing epoxy. Since the planar size of the buffer zone is smaller than that of the chip, the contamination of golden fingers and bonding pads due to the poor control of epoxy can be avoided, and furthermore the yield problems resulted from failed wire bonding and poor soldering are avoided. The assembly structure can be further applied to vertical stacking of multiple chips. A packaging method for the chip scale package is also provided.
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