Debugging a circuit using a circuit simulation verifier
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United States of America Patent
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Issued Date -
Nov 30, 2006
app pub date -
May 18, 2005
filing date -
May 18, 2005
priority date (Note) -
Abandoned
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Abstract
A circuit is tested using a device under test, a circuit simulator, and a circuit simulation verifier. Executing the verifier drives the simulator and collects trace information. This trace information enables the verifier to be executed backwards to a past execution point or clock cycle. The internal state of the verifier's execution is reconstructed at the past point. A state of verifier execution includes values of variables (including any ports or clocks) and an execution point (e.g., which code statement was last executed). A past state of execution can be determined by using trace information to modify the current state of execution. After a line of trace information has been processed, the 'current' state of verifier execution becomes the previous state as modified based on the trace information.
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