Vertical nanotransistor, method for producing the same and memory assembly
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Nov 23, 2006
app pub date -
Aug 16, 2004
filing date -
Aug 21, 2003
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A vertical nano-transistor having a source region, a drain region, a gate region and a semiconductor channel region between the source region and the drain region, the gate region being constituted by a metal film into which the transistor is embedded in such a manner that the gate region and the semiconductor channel region form a coaxial structure, the source region, the semiconductor channel region and the drain region being disposed vertically, and the gate region being electrically insulated from the source region, the drain region and the semiconductor channel region. The invention also relates to a method of producing the inventive transistor and a memory assembly.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully