System and method for vertically stacking computer memory components
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United States of America Patent
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Issued Date -
Nov 16, 2006
app pub date -
Apr 13, 2006
filing date -
Apr 19, 2001
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
System and method for vertically interconnecting a plurality of chips to provide increased volume circuit density for a given surface chip footprint. One embodiment provides a chip stack where two smaller chips are interconnected to a larger third chip on both sides thereof with the lower smaller chip flipped and connected below the larger chip. Further, in another embodiment, interconnecting structures extend from the larger chip beyond the extent of the lower smaller chip to facilitate the electronic connection of the chip stack with other computer components or circuit board. Another embodiment provides a method for stacking chips where two smaller chips are interconnected to a larger third chip on both sides thereof with the lower smaller chip flipped and connected below the larger chip.
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