Semiconductor structures having via structures between planar frontside and backside surfaces and methods of fabricating the same
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United States of America Patent
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Issued Date -
Nov 9, 2006
app pub date -
May 3, 2005
filing date -
May 3, 2005
priority date (Note) -
Abandoned
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Abstract
Methods of backside planarization processes have been developed to gain a high resolution backside process lithography and to make possible the development of dual faced MMICs and circuits. Two different processes have been employed to planarize via structures of various depths, one including epoxy-fill via structures with depths of 10 mils and the other solid-metal via structures with depths of 3.5 mils. Application of a wafer fabricated using methods of the present invention has been demonstrated in a monolithic circuit, where bias control to the frontside of the wafer was established by solder bumps on the planarized backside surface of a wafer including epoxy-filled via structures.
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