Fully buffered DIMM architecture and protocol
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United States of America Patent
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Issued Date -
Nov 2, 2006
app pub date -
May 2, 2005
filing date -
May 2, 2005
priority date (Note) -
Abandoned
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Abstract
A FB DIMM architecture and protocol comprises a memory controller, which is serially-connected to first and second DIMMs via southbound (SB) and northbound (NB) data paths to form a first channel, and to third and fourth DIMMs via SB and NB paths to form a second channel. Each DIMM comprises a plurality of RAM devices, and an AMB device arranged to receive data from the SB and NB paths, to encode/decode data for each of the DIMM's RAM devices, and to redrive data received from the SB or NB paths to the next device on the respective data paths. The system's protocol is arranged such that the bits of any given data word are interleaved across the RAM devices such that each RAM stores no more than one bit of the data word.
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