Dynamically reconfigurable processor
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United States of America Patent
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Issued Date -
Oct 26, 2006
app pub date -
Nov 4, 2005
filing date -
Nov 30, 2004
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Disclosed is a technology of generating an instruction set architecture (hereinafter, referred to as `ISA`) and a series of logic circuit configuration information of a processor for executing an application program from an application program described in a high-level language. The present invention also relates to a custom LSI development platform technology which can design, develop, and manufacture the application specific custom LSI in a short time by applying the generated ISA and logic circuit configuration information to a dynamic logic circuit reconfigurable processor. Furthermore, disclosed is a dynamically reconfigurable processor, which is reconfigurable using the generated logic circuit configuration information. Associated methods are also disclosed.
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