Vertical nanotransistor, method for producing the same and memory assembly
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United States of America Patent
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Issued Date -
Oct 12, 2006
app pub date -
Aug 16, 2004
filing date -
Aug 21, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A vertical nano-transistor having a source contact, a drain contact, a gate region and a semiconductor cylindrical channel region between the source contact and the drain contact, the cylindrical channel region being embedded in a flexible insulating substrate and in the upper section of the channel region, in such a manner that the gate region and the upper section of the channel region form a coaxial structure and that the source contact, the semiconductor channel region and the drain contact are disposed vertically and the gate region is electrically insulated from the source contact, the drain contact and the semiconductor channel region and the upper surface and lower surface of the substrate are provided with an electrical insulation. The invention also relates to a memory assembly which consists of a plurality of vertical nano-transistors of the above-mentioned type, and to a method of fabricating the same.
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