Tunneling-enhanced floating gate semiconductor device
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United States of America Patent
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Issued Date -
Oct 5, 2006
app pub date -
May 19, 2005
filing date -
Mar 30, 2005
priority date (Note) -
Abandoned
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Abstract
Tunneling-enhanced, floating gate semiconductor devices and methods for forming such devices are described. In one embodiment, a p-n junction device is formed with a floating gate that is partially doped with n- and p-type impurities. Two regions on either side of an n+ doped region in the floating gate and a surface region on a substrate are implanted with the impurities based on a number of predetermined configurations. In another embodiment, a transistor type semiconductor device is configured with implanted impurities in two regions of its floating gate as well as two surface regions in its substrate. Enhanced tunneling junction enables use of lower tunneling voltages in applications such as programming NVM cells.
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