Method of fabricating electrically conducting vias in a silicon wafer
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United States of America Patent
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Issued Date -
Jun 15, 2006
app pub date -
Dec 9, 2004
filing date -
Dec 9, 2004
priority date (Note) -
Abandoned
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Abstract
One or more electrically conducting vias are formed through a silicon substrate having a first surface, an opposite second surface, and a thickness between the first and second surfaces. A conductive metallic material is deposited on the first surface of the silicon substrate. For example, the metallic material may be deposited at one or more depressions in the first surface at one or more desired via locations. The conductive metallic material is migrated through the silicon substrate from the first surface to the second surface. For example, the conductive metallic material may be thermally migrated, and an oxide layer at the second surface may by used to terminate the migration.
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