Varactor
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United States of America Patent
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Issued Date -
Jun 15, 2006
app pub date -
Dec 9, 2004
filing date -
Dec 9, 2004
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A varactor having a capacitance includes a depletion mode transistor having a gate, a source, and a drain and an enhancement mode transistor also having a gate, a source, and a drain. The gates of the depletion mode transistor and the enhancement mode transistor are coupled together, the sources of the depletion mode transistor and the enhancement mode transistor are coupled together, and the drains of the depletion mode transistor and the enhancement mode transistor are coupled together. The enhancement mode transistor has a p/n junction. A bias source is coupled to the gates and the sources and drains so as to control the capacitance.
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