Dual work function gate in CMOS device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Jun 15, 2006
app pub date -
Dec 9, 2004
filing date -
Dec 9, 2004
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A transistor has a first silicon layer comprising a source region and a drain region separated by a channel region. A gate oxide is formed over the first silicon layer. A second silicon layer is formed over the gate oxide and comprises a dual work function gate. The dual work function gate may include p+ and n+ gate regions such that the transistor has different threshold voltages.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully