Failure test method for split gate flash memory
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United States of America Patent
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May 23, 2006
Grant Date -
May 11, 2006
app pub date -
Nov 4, 2004
filing date -
Nov 4, 2004
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Abstract
A failure test method of word line-bit line short circuit in a split gate flash memory is provided. A well leakage-current test is performed to identify a sector with a failed memory cell. After being programmed, memory cells in the sector undergo a first read operation to generate a first bit map of the sector. After being erased, these memory cells in the sector undergo a second read operation to generate a second bit map of the sector. The first bit map and the second bit map are overlaid to identify the actual address of the failed memory cell.
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