Nanoheteroepitaxy of Ge on Si as a foundation for group III-V and II-VI integration
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United States of America Patent
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Issued Date -
Apr 6, 2006
app pub date -
Oct 28, 2005
filing date -
Sep 8, 2004
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Abandoned
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Abstract
A method of forming a virtually defect free lattice mismatched nanoheteroepitaxial layer is disclosed. The method includes forming an interface layer on a portion of a substrate. The interface layer can be, for example, SiO.sub.2, Si.sub.3N.sub.4, Al.sub.2O.sub.3, or W. A template can then be made by forming a plurality of touchdown windows in the interface layer. A plurality of seed pads can then be formed in the touchdown windows by exposing the interface layer to a material comprising a semiconductor material. The plurality of seed pads, having an average width of about 1 nm to 10 nm, can be interspersed within the interface layer and contact the substrate. A first layer is formed by lateral growth of the seed pads over the interface layer. A second layer is then formed on the first layer. The second layer can be for example, one of a Group III-V and II-VI heteroepitaxial film.
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