Memory

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United States of America Patent

SERIAL NO

11281492

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Abstract

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A memory capable of suppressing disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, and applies prescribed reverse voltages to at least non-selected first storage means connected to a non-selected word line substantially identical times respectively or substantially applies no voltage through a read operation and a rewrite operation.

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Patent Owner(s)

Patent OwnerAddress
PATRENELLA CAPITAL LTD LLC1209 ORANGE STREET WILMINGTON DE 19801

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Sakai, Naofumi Anpachi-gun, JP 16 259
Takano, Yoh Ogaki-shi, JP 28 311

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