Importance

Loading Importance Indicators...

Abstract

A memory module capable of exhibiting reduced input clock skew. More particularly, an unbuffered memory module that comprises a substrate, multiple memory components mounted to the substrate, and input/output and address and command bus connectors that transmit digital information to and from the memory components further includes a phase lock loop (PLL) circuit that electrically interconnects a clock-in connector to the memory components for generating and transmitting a module clock signal to the memory components without routing any information to the memory components through a register. In this manner, the PLL operates to provide the memory module with an onboard clock generator that synchronizes the memory components of the module.

Loading the Abstract Image...

First Claim