Stacked chip package with exposed lead-frame bottom surface
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United States of America Patent
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Issued Date -
Feb 9, 2006
app pub date -
Aug 9, 2004
filing date -
Aug 9, 2004
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A stacked chip package with exposed lead-frame bottom surface is disclosed. The stacked chip package includes a first die encapsulated in an encapsulated molding compound, which is mounted on an active surface of a second die. A bottom surface of the second die is mounted to a top surface of a die supporting section of the lead-frame. The bottom surface of the die supporting section is exposed outside the encapsulated molding compound. A plurality of bonding wires electrically interconnect the die pads of the first die and the second die to the corresponding lead fingers. Moreover, each lead finger of the lead-frame is preferably formed with a deflected structure with a bent section, which enables the dimension size of the stacked chip package to get more compact.
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