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Abstract

A compact, differential clock input buffer that converts single-end or differential sine wave or square wave inputs into complementary squarewave digital outputs, with low-jitter, and 50% duty cycle outputs. Low-noise oscillator design concepts are applied to provide at least two stages of regeneration. This minimizes the time the clock buffer spends in the noise-susceptible linear region. A first stage latching circuit consists of a pair of cross coupled transistors (i.e., a differential transistor pair) with resistive loads to provide gain, limiting, hysteresis, and latching functions. These transistors operate in a linear region for only a very small range of input voltage. A second stage latching circuit, which can use a current mirror, is also provided as a pair of cross coupled transistors with resistive loads. The second stage latch provides positive feedback to further limit the linear operating range.

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First Claim