Expanding architecture for error correction code and method for the same
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United States of America Patent
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Issued Date -
Dec 29, 2005
app pub date -
Jun 23, 2004
filing date -
Jun 23, 2004
priority date (Note) -
Abandoned
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Abstract
An expanding error correction architecture groups the output data of a data end to several parts, and each grouped output data of the data end is connected to one of a plurality of error correction circuit to be processed for a check sum. One part of the output data of the data end is arranged in a successive form, and another part of the output data of the data end is arrange in a non-successive form. The architecture of the present invention increases the error detection ability for check sums of different data sizes in the data end.
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