Data reading structure
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United States of America Patent
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N/A
Issued Date -
Dec 22, 2005
app pub date -
Jun 16, 2004
filing date -
Jun 16, 2004
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A data reading structure for a 8-bit microprocessor to read several bytes of data at a time has a memory module and a selector module. The memory module has a first memory having a first and second data output ports and a second memory has a third and fourth data output ports. The selector module has a first data selector, a second data selector and a third data selector. The first, second and third data selectors respectively select one output from the first, second, third and fourth data output ports. Thereby, the microprocessor is allowed to read successively three bytes of data from an output terminal of the selector module during a memory read cycle to reduce the fetch time of an instruction.
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