Memory circuit
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United States of America Patent
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N/A
Issued Date -
Dec 8, 2005
app pub date -
Jun 8, 2004
filing date -
Jun 8, 2004
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A memory circuit is designed for a Universal Serial Bus (USB) 2.0 circuit architecture. An analog front end unit is connected to a high-speed delay phase lock loop unit. A full-speed delay phase lock loop and data recovery unit is connected to the analog front end unit. A receiver unit is connected to the high-speed delay phase lock loop unit and the full-speed delay phase lock loop and data recovery unit. A transceiver unit is connected to the analog front end unit and the receiver unit. A control unit is connected to the transceiver unit, the receiver unit, the high-speed delay phase lock loop unit and the full-speed delay phase lock loop and data recovery unit. An external oscillator unit is connected to the control unit.
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