Surface-mount chip-scale package
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United States of America Patent
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Issued Date -
Dec 8, 2005
app pub date -
Jun 7, 2004
filing date -
Jun 7, 2004
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A chip-scale package and method of manufacturing a chip-scale package are provided. The chip-scale package includes a mounting portion defined by a plurality of metal layers formed on each of a plurality of semiconductor regions for mounting a device thereto. The mounting portions are formed on a first side of the plurality of semiconductor regions. The chip-scale package further includes a backside metal surface formed on each of a second side of the plurality of semiconductor regions, with the plurality of semiconductor regions providing electrical connection between the mounting portions and the backside metal surfaces.
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