Integrated via resistor
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United States of America Patent
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Issued Date -
Dec 1, 2005
app pub date -
May 28, 2004
filing date -
May 28, 2004
priority date (Note) -
Abandoned
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Abstract
A method of forming a resistor in an integrated circuit, comprising etching a first via in a first layer of dielectric material, depositing a layer of metal adjacent the first layer of dielectric material, depositing a second layer of dielectric material adjacent the layer of metal, and etching a second via in the second layer of dielectric material, said second via electrically connected in series to the first via by way of the layer of metal to form said resistor.
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