Method and apparatus for formal circuit verification
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United States of America Patent
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app pub date -
Jul 26, 2005
filing date -
Jan 30, 2003
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Abandoned
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Abstract
A method and apparatus for determining the time behavior of a digital circuit based on a starting assumption is disclosed. Generally, in a formal verification of a digital circuit, the time behavior of a digital circuit is monitored to verify or refute whether formulated properties, which comprise an assumption and an assertion, result as a consequence of a presence of an assumption in the digital circuit. In order to determine the behavior of the digital circuit, the time behavior of the digital circuit is examined from a starting initial state of the digital circuit. A relevant auxiliary property is activated and the assertion of the auxiliary property is added to the digital circuit. The digital circuit is then monitored over a period of time.
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