Semiconductor molding method and structure
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United States of America Patent
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Issued Date -
Nov 24, 2005
app pub date -
May 18, 2004
filing date -
May 18, 2004
priority date (Note) -
Abandoned
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Abstract
A semiconductor molding method and structure, wherein a chip carrier is mounted with a plurality of semiconductor chips thereon, and encapsulation bodies are fabricated on the chip carrier to form a plurality of package units for respectively encapsulating the semiconductor chips. At least one pair of adjacent package units are connected together by at least one connective portion made of the encapsulation body, so as to prevent the semiconductor molding structure from warpage and deformation.
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