Semiconductor molding method and structure

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20050258552A1
SERIAL NO

10848648

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Calculated Rating
US Family Size
Non-US Coverage

Abstract

See full text

A semiconductor molding method and structure, wherein a chip carrier is mounted with a plurality of semiconductor chips thereon, and encapsulation bodies are fabricated on the chip carrier to form a plurality of package units for respectively encapsulating the semiconductor chips. At least one pair of adjacent package units are connected together by at least one connective portion made of the encapsulation body, so as to prevent the semiconductor molding structure from warpage and deformation.

First Claim

See full text

Other Claims data not available

Family

PCTEP
+
−
  • No Family data available.

Patent Owner(s)

Patent OwnerAddress
ULTRATERA CORPORATIONNO 2 LI-HSIN RD 3 SCIENCE-BASED INDUSTRIAL PARK HSINCHU

International Classification(s)

loading....
  • 2004 Application Filing Year
  • H01L Class
  • 14681 Applications Filed
  • 9246 Patents Issued To-Date
  • 62.98 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances2004200520062007200820092010201120122013201420152016201720182019202020210255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kim, Sung Jin Hsin-Chu, TW 350 2734

Cited Art Landscape

Load Citation

Patent Citation Ranking

  • 2 Citation Count
  • H01L Class
  • 2.00 % this patent is cited more than
  • 20 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges56113063435821410785533224218401 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +05010015020025030035040045050055060065070075080085090095010001050110011501200

Forward Cite Landscape

Load Citation