Masking circuit and method of masking corrupted bits

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20050240848A1
SERIAL NO

11109844

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Abstract

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A masking circuit for selectively masking scan chain inputs and/or outputs during scan testing of an integrated circuit, comprises a mask register having at least two mask register elements for each scan chain to provide a plurality of masking modes; and an input and output mask control circuit for each scan chain, each mask control circuit being connected between a test pattern source and a signature register and between a serial input and a serial output of an associated scan chain and being responsive to mask control data stored in the register elements for configuring the associated scan chain in one of the plurality of masking modes during a scan test of the circuit.

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Patent Owner(s)

Patent OwnerAddress
LOGICVISION INC25 METRO DRIVE THIRD FLOOR SAN JOSE CA 95110

International Classification(s)

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  • 2005 Application Filing Year
  • G01R Class
  • 3208 Applications Filed
  • 1809 Patents Issued To-Date
  • 56.40 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances20052006200720082009201020112012201320142015201620170255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cote, Jean-Francois Chelsea, CA 26 411
Nadeau-Dostie, Benoit Gatineau, CA 53 1534
Price, Paul Stoughton, MA 36 379

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  • 21 Citation Count
  • G01R Class
  • 78.12 % this patent is cited more than
  • 20 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges224251927133171567981301 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +0255075100125150175200225250275300325350375400425450

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