Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancements

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United States of America Patent

APP PUB NO 20050229130A1
SERIAL NO

10820260

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Abstract

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An automated design for manufacturability platform for integrated physical verification and manufacturing enhancement operations. Given original layouts and one or more associated resolution-enhanced layouts, intermediate resolution-enhancement state layouts are reconstructed, and selective localized resolution-enhancement reconfigurations, modifications, and/or perturbations are introduced on any existing enhancements in order to improve manufacturability and yield.

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Patent Owner(s)

Patent OwnerAddress
RPX CORPORATIONFOUR EMBARCADERO SUITE 4000 SAN FRANCISCO CA 94111

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hung, Meg Saratoga, CA 3 407
Tang, Hongbo San Jose, CA 7 970
Wang, Xin Sunnyvale, CA 1487 14353
Wu, Shao-Po Portola Valley, CA 18 566

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