Circuit and method for enhanced low frequency switching noise suppression in multilayer printed circuit boards using a chip capacitor lattice
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United States of America Patent
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Issued Date -
Oct 13, 2005
app pub date -
Mar 17, 2004
filing date -
Mar 17, 2004
priority date (Note) -
Abandoned
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Abstract
A printed circuit board (PCB) uses arrays of chip capacitors over the entire surface of the PCB. The PCB includes an upper conductive surface routing signals to components of the PCB, a lower conductive surface, vias between the upper and lower surfaces, and a layer of patches disposed between the upper and lower surfaces to which the vias and chip capacitors are connected. The chip capacitors connect the vias to the upper conductive surface. The use of chip capacitors in a periodic lattice extends the frequency range for suppressing noise in power planes of isolated capacitors from several hundred MHz or less to 4 GHz. Combining the capacitors along with the buried patches extends the low frequency cutoff of high frequency reference noise suppression circuits to 50 MHz or less.
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