Method and circuit for determining a slow clock calibration factor
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Oct 6, 2005
app pub date -
Apr 6, 2004
filing date -
Apr 6, 2004
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
Shown is a method and circuit for determining a calibration factor between a fast, high accuracy clock signal and a slow, low accuracy clock signal, which can be realised with a minimum number of electronic units, and which obtains the calibration factor in a very short time, thus minimising power consumption of the circuit. The present invention operates by counting the number of cycles of a high accuracy clock signal during a single cycle of a low accuracy clock signal to obtain a first number representing the number of cycles counted and then successively summing the first number until a sum of the first numbers reaches a first predetermined value. The count of the number of summing operations required to reach the first predetermined value is then used to determine the calibration parameter, which is proportional to the number of summing operations.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully