Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure
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United States of America Patent
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app pub date -
Jun 3, 2005
filing date -
Jul 10, 1997
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Abandoned
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Abstract
A wiring structure to effectively reduce the wiring capacitance, and a method of forming the wiring structure is disclosed. In one embodiment, an underlying film having a dielectric constant than that of silicon oxide is formed on at least on side surfaces of the wires of a wiring layer and a low dielectric constant film having a further lower dielectric constant is formed between the wires. Further the surfaces of the underlying film are positively sloped. Because the low dielectric constants of the underlying film and the low dielectric constant film, the wiring capacitance is effectively reduced. Further, the positively sloped surfaces facilitate the filling of narrow spaces between the wires by the low dielectric constant film.
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