Area efficient realization of coefficient architecture for bit-serial fir, IIR filters and combinational/sequential logic structure with zero latency clock output
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United States of America Patent
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app pub date -
Oct 21, 2004
filing date -
Oct 13, 1998
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Abandoned
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Abstract
An area-efficient realization of a coefficient block [A] or architecture [A] with hardware sharing techniques and optimizations applied to this block. The block [A] is connected to coefficient lines coming from block [E] and/or [F], to be connected to perform filtering operation or a mathematical computing operation with optimization in hardware and to provide a zero latency output. Also provided is area minimal realization of digital filters based on coefficient block [A] when operated in bit serial fashion. The optimization techniques and structure applicable to linear digital filters typically a finite impulse response filter, infinite impulse response filter and for other filters and applications based on combinational logic consisting of a delay element, a multiplier, an adder and a subtractor.
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