Selective epi-region method for integration of vertical power MOSFET and lateral driver devices
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United States of America Patent
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Issued Date -
Jul 7, 2005
app pub date -
Jan 6, 2004
filing date -
Jan 6, 2004
priority date (Note) -
Abandoned
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Abstract
A semiconductor device has a driver device (10) in proximity to a power device (12). In making the semiconductor device, an N+ layer (24) is formed on a substrate (22). A portion of the N+ layer is removed, substantially down to the substrate, to provide a layer offset (28) between the driver device area and the power device area. An epi region of uniform thickness is formed over the driver device and power device areas. The epi region has a similar offset as the layer offset. The epi region is planarized so that the epi region over the power device area has less thickness than the epi region over the driver device area. The driver devices are formed in first and second wells (36, 38) in the thicker area of the epi region. The power device is formed in the third well (40) in the thinner area of the epi region.
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