Processor including branch prediction mechanism for far jump and far call instructions
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United States of America Patent
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N/A
Issued Date -
Jun 30, 2005
app pub date -
Oct 22, 2002
filing date -
Oct 23, 2001
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method and apparatus are provided for processing far jump-call branch instructions to increase the efficiency of a processor pipeline. The processor includes a far jump-call target buffer which stores the default address/operand size corresponding to each of a plurality of previously executed far jump-call instructions. When a far jump-call instruction is encountered, it is speculatively executed using the corresponding default address/operand size for that instruction as stored in the far jump-call target buffer. This speculative far jump-call instruction is executed and resolved thus determining the actual address/operand size. If the actual address/operand size matches the speculative default address/operand size then the speculation was correct and processing continues. However, if there is no match, then the speculation was wrong and the pipeline is flushed.
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