Various structure/height bumps for wafer level-chip scale package
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United States of America Patent
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Issued Date -
Jun 23, 2005
app pub date -
Dec 19, 2003
filing date -
Dec 19, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A die comprising: a substrate; two or more various shaped bump structures having a solder line formed over the substrate; and an epoxy layer formed over the substrate. The epoxy layer having a top surface wherein: (a) the solder lines are below the top surface of the epoxy layer'; (b) the solder lines are above the top surface of the epoxy layer; or (c) some of the solder lines are below the top surface of the epoxy layer and some of the solder lines are above the top surface of the epoxy layer.
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