Flip chip package using no-flow underfill and method of fabrication
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United States of America Patent
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Issued Date -
Apr 28, 2005
app pub date -
Oct 22, 2003
filing date -
Oct 22, 2003
priority date (Note) -
Abandoned
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Abstract
A design and method of fabrication for a semiconductor package is described. A solder bumped semiconductor chip is assembled to a metallized package substrate utilizing the solder bumps. The interconnecting solder bumps are properly constrained at assembly by the introduction of a no-flow underfill between the chip and the substrate. The no-flow underfill constrains the solder of the solder bumps so as to maintain the desired size and shape.
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