System and method for implementing a NAND memory interface
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United States of America Patent
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Issued Date -
Apr 21, 2005
app pub date -
Oct 17, 2003
filing date -
Oct 17, 2003
priority date (Note) -
Abandoned
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Abstract
A system and method for implementing a NAND memory interface for an embedded PC system are disclosed. The system and method include a NAND interface device adapted to be coupled to a first chip select of a dedicated SDRAM bus, and at least one NAND memory device coupled to the NAND interface device. The first chip select is utilized to access the NAND memory device via the NAND interface device. Accordingly, the NAND interface device and the at least one NAND memory device function substantially as a hard disk in the embedded PC system. As a result, lower costs for non-volatile memory are achieved while increasing speed and decreasing motherboard PCB real estate requirements.
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