Method and structure for compact transistor array layout
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United States of America Patent
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Issued Date -
Apr 21, 2005
app pub date -
Apr 28, 2004
filing date -
Oct 17, 2003
priority date (Note) -
Abandoned
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Abstract
A method and structure for a compact transistor array layout is applied in a bipolar transistor integration process for equalizing distributed reactance in a wafer. The structure has a plurality of unitization elements with a first element and a second element for receiving an input signal. The first element and the second element are composed of a plurality of transistors. A plurality of wires used to feed the input signal in the unitization elements are arranged in multi-level branches manner. The wires can have predetermined resistance, capacitance, or inductance and the input signal is equidistant from the unitization elements. A multi-dimensional layout space is formed by arranging the unitization elements in order. The inventive structure can be applied in heterojunction bipolar transistor (HBT) or bipolar junction transistor (BJT) so that more transistors can be installed in a unit volume.
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