Memory module and memory support module
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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N/A
Issued Date -
Mar 31, 2005
app pub date -
Aug 5, 2004
filing date -
Aug 8, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
It is aimed at not only enabling access to an inaccessible SDRAM area from a PC which only outputs A0 through A11 signals, but also making a common memory module connectable to earlier or latest PCs independently of their models. According to the construction, a connected PC (computer) inputs a high-order address signal A12. It is determined whether or not the input A12 signal is set to a state different from an unused state. A determination signal is generated so as to indicate a state corresponding to a determination result. When the determination signal indicates a changed state, the PC inputs A0 through A12 signals and supplies them to a memory chip 20. When the determination signal indicates an unchanged state, the PC inputs A0 through A11 signals and a select signal. The A12 signal is generated based on the input select signal. The memory chip 20 is supplied with the A12 signal and the input A0 through A11 signals.
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