Method and apparatus for reducing on-chip memory in vertical video processing
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United States of America Patent
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Issued Date -
Mar 24, 2005
app pub date -
Mar 17, 2003
filing date -
Jul 23, 1998
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A digital image processor includes an input buffer for storing raster-scanned data. A slice-buffer memory is coupled to the input buffer to store a portion of a vertical slice of said raster-scanned data. The vertical slice is processed by a vertical slice processor having an input coupled to the slice-buffer memory. The vertical slice processor reassembles the vertical slices into processed raster-scanned data in an output buffer that is coupled to the output of the vertical slice processor. The digital image processor preferably utilizes multiple sequential processing stages and processes the raster-scanned data along the horizontal axis of the vertical slices.
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