Stacked-chip semiconductor package and fabrication method thereof
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United States of America Patent
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Issued Date -
Mar 3, 2005
app pub date -
Aug 26, 2003
filing date -
Aug 26, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A stacked-chip semiconductor package and a fabrication method thereof are provided in which a thermal blocking member is applied over an opening formed through a chip carrier, with a first chip being mounted on the thermal blocking member and a second chip being attached oppositely to the thermal blocking member and received within the opening; the first and second chips are electrically connected to the chip carrier by bonding wires. An encapsulant is formed on the chip carrier for encapsulating the second chip and having a cavity for receiving and exposing the first chip that is a light sensitive chip. By the thermal blocking member interposed between the first and second chips, heat produced from the second chip is prevented from passing to the first chip, thereby not damaging the first chip or causing warpage of the first chip, which can thus assure reliable performances of the semiconductor package.
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