Resource utilization mechanism for microprocessor power management
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United States of America Patent
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Issued Date -
Feb 24, 2005
app pub date -
Aug 22, 2003
filing date -
Aug 22, 2003
priority date (Note) -
Abandoned
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Abstract
A microprocessor apparatus is provided including multiple functional units, some of which can enter a power reduction mode to decrease overall power consumption when needed. The functional units generate respective activity signals to indicate the level of activity of each of the functional units. The activity outputs are monitored by utilization assessment logic to determine a current total power consumption value for the microprocessor. The microprocessor is capable of successively entering a series of power reduction modes when the current total power consumption value is greater than a threshold power value of a specified power profile.
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