Multi-bit vertical memory cell and method of fabricating the same
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United States of America Patent
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Issued Date -
Feb 10, 2005
app pub date -
Feb 10, 2004
filing date -
Aug 8, 2003
priority date (Note) -
Abandoned
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Abstract
A multi-bit vertical memory cell and method of fabricating the same. The multi-bit vertical memory cell comprises a semiconductor substrate with a trench, a plurality of bit lines formed therein near its surface and the bottom trench respectively, a plurality of bit line insulating layers over each bit line, a silicon rich oxide layer conformably formed on the sidewall of the trench and the surface of the surface of the bit line insulating layer, and a word line over the silicon rich oxide layer, and the trench is filled with the word line.
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