PMOS memory cell
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United States of America Patent
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app pub date -
Sep 7, 2004
filing date -
Sep 16, 2002
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Abandoned
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Abstract
A single-poly PMOS nonvolatile memory (NVM) cell and a method of programming, erasing and reading such a cell are implemented using a single-poly PMOS NVM cell which includes a floating gate injection transistor, a select switch, and a tunneling capacitor having one plate in common with the floating gate of the injection transistor. Methods of altering the number of electrons on the floating gate of the single-poly PMOS NVM cell are used which, with appropriate biasing of the components permit the power terminals of the cell to have appropriate voltages applied to thereby avoid stuck bits and induce hot electrons onto the floating gate of the NVM cell.
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