Processor interface for test access port
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United States of America Patent
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N/A
Issued Date -
Feb 3, 2005
app pub date -
Jul 16, 2004
filing date -
Aug 1, 2003
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A processor interface for test access port comprises a write buffer for storing data output by a processor and having a command field, a data field, and a serial output connected to a serial input of the test access port, a read buffer for storing data output by the test access port for access by the processor and having a data field, and a serial input connected to a serial output of the test access port; and a control circuit responsive to a command stored in the command field for generating test access port control signals for transferring test data from the write buffer to the test register and from the test register to the read buffer via test access port serial input and serial output.
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