Dummy structures to reduce metal recess in electropolishing process
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United States of America Patent
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Issued Date -
Dec 16, 2004
app pub date -
Jul 27, 2004
filing date -
Aug 23, 2001
priority date (Note) -
Abandoned
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Abstract
A semiconductor structure for providing metal interconnections (140) and a method for electropolishing a metal layer on a semiconductor structure. A semiconductor structure includes a dielectric layer (151) with recessed areas (151r) and non-recessed areas (151n), a metal layer formed on the structure fills the recessed areas to form interconnection lines, and a plurality of dummy structures (130) placed adjacent the interconnect lines. The method includes forming a dielectric layer with recessed and non-recessed areas on a semiconductor wafer. Forming dummy structures adjacent the recessed areas. Forming a metal layer to cover the dielectric layer and the dummy structures. The metal layer is then electropolished to expose the non-recessed area.
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