Forming a semiconductor structure using a combination of planarizing methods and electropolishing
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United States of America Patent
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app pub date -
Aug 10, 2004
filing date -
Aug 18, 2001
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Abstract
A method for planarizing and electropolishing a conductive layer on a semiconductor structure includes forming a dielectric layer with recessed areas and non-recessed areas on the semiconductor wafer. A conductive layer is formed over the dielectric layer to cover the recessed areas and non-recessed areas. The surface of the conductive layer is then planarized to reduce variations in the topology of the surface. The planarized conductive layer is then electropolished to expose the non-recessed area.
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