Method for manufacturing a bipolar transistor using a CMOS process
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United States of America Patent
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Issued Date -
Dec 16, 2004
app pub date -
Mar 16, 2004
filing date -
Apr 1, 2003
priority date (Note) -
Abandoned
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Abstract
A method of forming a bipolar junction transistor using a CMOS process that includes performing a high voltage deep well and drive-in process in a semiconductor substrate having a predetermined substructure; performing a local oxidation of silicon (LOCOS) process; performing an Nbase and Pbase process on the resulting structure; forming logic N well and P well and annealing the logic wells; forming a poly gate and sequentially forming NMOS/PMOS LDD source/drain; and forming N+/P+ source/drain, annealing the source/drain and sequentially performing a CONT.about.PAD process.
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