Integrated self-testing of a reconfigurable interconnect
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United States of America Patent
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Issued Date -
Nov 11, 2004
app pub date -
May 5, 2003
filing date -
May 5, 2003
priority date (Note) -
Abandoned
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Abstract
Methods and systems for increasing the speed with which configuration data can be loaded and tested on a reconfigurable interconnect device are disclosed. A reconfigurable interconnect integrated circuit (IC), or a reconfigurable portion of an integrated circuit, is coupled to a digital storage circuit such as a shift register. A seed configuration pattern is loaded once into the digital storage circuit, which is loaded onto a first set of switches in the integrated circuit. The shift register shifts the configuration patterns by a predetermined amount, and then loads the shifted configuration pattern onto a second set of switches in the integrated circuit. Using the digital storage circuit coupled to the reconfigurable interconnect, each integrated circuit only needs to load a configuration pattern once, instead of reloading a new configuration pattern for each set of switches in the integrated circuit.
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