Through-via vertical interconnects, through-via heat sinks and associated fabrication methods
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United States of America Patent
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Issued Date -
Oct 14, 2004
app pub date -
Apr 29, 2004
filing date -
Aug 24, 2001
priority date (Note) -
Abandoned
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Abstract
An improved through-via vertical interconnect, through-via heat sinks and associated fabrication techniques are provided for. The devices benefit from an organic dielectric layer that allows for low-temperature deposition processing. The low-temperature processing used to form the through-via interconnects and heat sinks allows for the formation of the interconnects and heat sinks at any point in the fabrication of the semiconductor device, including post-formation of active devices and associated circuitry. The through-via vertical interconnects of the present invention are fabricated so as to insure conformal thickness of the various layers that form the interconnect constructs. As such, the interconnects can be formed with a high aspect ratio, in the range of about 4:1 to about 10:1, substrate thickness to interconnect diameter.
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